1. Field of the Invention
The present invention relates to an integrated circuit device which has an integrated circuit and a plurality of pads for receiving and outputting signals to the integrated circuit, and a wiring board of the integrated circuit device. More particularly, the present invention relates to an integrated circuit device, such as a tape carrier package, a semiconductor chip or an electronic device, and a wiring board, such as a tape carrier or a printed wiring board.
2. Description of the Related Art
Signal input and output between a probe card and a semiconductor integrated circuit are carried out through pads. For example, signal input and output between a semiconductor chip mounted on a TCP (Taper Carrier Package), such as a TAB (Tape Automated Bonding) or COF (Chip On Film), and a probe card are carried out through pads provided on the base film of the TCP. Signal input and output between an integrated circuit, formed on a semiconductor chip, and a probe card are executed through pads provided on the semiconductor substrate.
The optimization of the layout of pads is important in ensuring easier contact of probes provided on the probe card with the pads. For example, Japanese Patent Laid-Open Publication No. 2002-196036 discloses a technique of laying out a plurality of pads in a direction inclined to the lengthwise direction of the semiconductor substrate which is mounted on the TCP in order to ensure easier contact of probes to pads on the TCP.
The prior art technique however has the following drawbacks. Recently, the number of signals to be input to and output from a semiconductor integrated circuit is increasing. Accordingly, the number of pads needed for signal input and output between a probe card and a semiconductor integrated circuit is increasing too. According to the technique described in Japanese Patent Laid-Open Publication No. 2002-196036, an increase in the number of pads enlarges the area of a region where pads are laid out in proportion to the number of pads.
However, an increase in the area of the pad-layout region in proportion to the number of pads undesirably leads to an increase in the cost for an integrated circuit device. For example, an increase in the area needed for layout of pads on a TCP increases the manufacture cost for the TCP. Likewise, an increase in the area needed for layout of pads on a semiconductor chip increases the manufacture cost for the semiconductor chip. Therefore, there is a demand of reducing the area needed for layout of pads.